A. Field of the Invention
This invention relates generally to data processing systems and more particularly to apparatus for enabling synchronization and information exchanges between independent asynchronous processors.
B. The Description of the Prior Art
As the complexity of modern data processing units has increased, more control functions formerly carried out by the central processing unit (CPU) subsystem are being delegated to other subsystems or processing units. For example, it is now common for an input/output controller (IOC) subsystem to have its own control store for carrying out its required control functions. In like manner, peripheral processors are now being designed with their own control store units. While each control apparatus provides the means for controlling the manipulation of its own processor, it may also provide the means for controlling manipulations which occur within another processor.
In the past, since these control apparatus and processing units were able to operate independently, adequate synchronization of operations was required. Further, much time was required for identifying and obtaining control information within the purview of the other processing unit. More specifically, in the past, the communication facilities for interprocessor communication would be utilized after one of the processors stored the information and then by a stimulus-response communication interchange indicated to the other processor the information's location. The other processor would then locate the information and retrieve it. In the situation wherein the central processing subsystem was involved, then main memory would be used to store the control information.
Alternatively, control information may be provided by software communication between the processing units. Not only does this slow overall operations of each processor, but in addition, it ties up main memory to a significant extent. Furthermore, the software is transmitted across the standard peripheral interface bus and as a result the speed of the actual data transfer is reduced. In view of the timing, synchronization and storage problems, it would be desirable to have a separate facility for directly transferring control information such that the time lags involved in interprocessor exchanges would be reduced.